November 2, 2020

Playing with FPGA (simulator)

Although I've wanted to try out FPGA for a long time, but never really had the chance/time to.  This is a note on learning/playing with FPGA.

In this posting, which is just the first step -- learning about it, and use simulator first.  If/when I decide to continue with this journey, I'll then buy a small FPGA board, and continue.

I've gathered the information by talking to some experts online, googling, and read a few books.


What is FPGA (Field Programmable Gate Array)

First, what FPGA is.  Watch this short video - only 1:25 long -

Or, read Wiki, https://en.wikipedia.org/wiki/Field-programmable_gate_array


Installing Simulator

There are several simulators, and someone suggested to use Icarus Verilog (http://iverilog.icarus.com/) as it is light. 

Environment: Ubuntu 20.04

I've originally downloaded the source code and compiled, but later found Ubuntu already has apt package ready.  

Reference video, https://www.youtube.com/watch?v=xd-ZvBJiv3M -- this is in Chinese, so no clue what the video uploader is saying, but you can just watch the video with steps.  I wrote the steps here to avoid watching the whole thing.

$ sudo apt-get install iverilog
$ sudo apt-get install gtkwave

 

Testing Simulator #1

1. Create project directory

$ mkdir verilog_test1

2. Using VSC, edit a file called "test1.v" in the directory created above:

module main;
initial
begin
$display("Hello world!");
$finish;
end
endmodule

3. compile the code

$ iverilog test1.v -o test1

4. Run it

$ vvp test1

 

Testing Simulator #2

This is from https://www.youtube.com/watch?v=3Xm6fgKAO94, and it also shows installing Icarus Verilog on Windows.

1. Create two files

hello.v:

// hello.v
module hello(A, B);

input A;
output B;
assign B = A;

endmodule

hello_tb.v:

// hello_tb.v

`timescale 1ns / 1ns
`include "hello.v"

module hello_tb;

reg A;
wire B;

hello uut(A, B);

initial begin
$dumpfile("hello_tb.vcd");
$dumpvars(0, hello_tb);

A = 0; // single bit
#20; // wait for 20ns, to view wave form

A = 1;
#20;

A = 0;
#20;

$display("Test complete");
end

endmodule


2. Compile and run

$ iverilog -o hello_tb.vvp hello_tb.v
$ vvp hello_tb.vvp
VCD info: dumpfile hello_tb.vcd opened for output.
Test complete


hello_tb.vvp file is created.

 

3. View wave

$  gtkwave hello_tb.vcd

or, File > Open Tab > and select "hello_tb.vcd"

In left nav, lower pane, select both reg A, wire B.  Then click on "Insert" button.

 

Learning Resources


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